• Kan Liang's avatar
    perf/x86: Add Meteor Lake support · 38aaf921
    Kan Liang authored
    From PMU's perspective, Meteor Lake is similar to Alder Lake. Both are
    hybrid platforms, with e-core and p-core.
    
    The key differences include:
    - The e-core supports 2 PDIST GP counters (GP0 & GP1)
    - New MSRs for the Module Snoop Response Events on the e-core.
    - New Data Source fields are introduced for the e-core.
    - There are 8 GP counters for the e-core.
    - The load latency AUX event is not required for the p-core anymore.
    - Retire Latency (Support in a separate patch) for both cores.
    
    Since most of the code in the intel_pmu_init() should be the same as
    Alder Lake, to avoid code duplication, share the path with Alder Lake.
    
    Add new specific functions of extra_regs, and get_event_constraints
    to support the OCR events, Module Snoop Response Events and 2 PDIST
    GP counters on e-core.
    
    Add new MTL specific mem_attrs which drops the load latency AUX event.
    
    The Data Source field is extended to 4:0, which can contains max 32
    sources.
    
    The Retire Latency is implemented with a separate patch.
    Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
    Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
    Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
    Acked-by: default avatarPeter Zijlstra <peterz@infradead.org>
    Link: https://lore.kernel.org/r/20230104201349.1451191-2-kan.liang@linux.intel.com
    38aaf921
perf_event.h 43.8 KB