• Heiko Carstens's avatar
    s390/fpu: fix VLGV macro · 39ceca15
    Heiko Carstens authored
    The VLGV macro generates the VLGV instruction and has a vr parameter which
    correlates to the V3 vector register field of the instruction (bits 12-15).
    Due to its position in the VRS-c instruction format of the VLGV
    instruction, this field correlates to the second bit of the RXB byte of the
    instruction (see Principles of Operation, Chapter "Vector Overview and
    Support Instructions").
    
    Within the VLGV macro the MRXBOPC macro is used to generate the RXB field
    of the instruction. The usage of the MRXBOPC macro is incorrect, since the
    vector register number is passed as third parameter (which correlates to
    the first bit of the RXB byte), while it should be passed as fourth
    parameter (second bit of the RXB byte). In result an incorrect instruction
    would be generated if the VLGV macro would be used for vector register
    numbers larger than 15.
    
    Fix this and pass the vector register number as fourth parameter.
    
    Currently there are no users within the kernel which use the macro in a way
    that broken code would be generated.
    Reviewed-by: default avatarJens Remus <jremus@linux.ibm.com>
    Reviewed-by: default avatarClaudio Imbrenda <imbrenda@linux.ibm.com>
    Reviewed-by: default avatarHendrik Brueckner <brueckner@linux.ibm.com>
    Signed-off-by: default avatarHeiko Carstens <hca@linux.ibm.com>
    39ceca15
vx-insn-asm.h 13.2 KB