• Will Deacon's avatar
    arm64: IPI each CPU after invalidating the I-cache for kernel mappings · 3b8c9f1c
    Will Deacon authored
    When invalidating the instruction cache for a kernel mapping via
    flush_icache_range(), it is also necessary to flush the pipeline for
    other CPUs so that instructions fetched into the pipeline before the
    I-cache invalidation are discarded. For example, if module 'foo' is
    unloaded and then module 'bar' is loaded into the same area of memory,
    a CPU could end up executing instructions from 'foo' when branching into
    'bar' if these instructions were fetched into the pipeline before 'foo'
    was unloaded.
    
    Whilst this is highly unlikely to occur in practice, particularly as
    any exception acts as a context-synchronizing operation, following the
    letter of the architecture requires us to execute an ISB on each CPU
    in order for the new instruction stream to be visible.
    Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    3b8c9f1c
cpu_errata.c 17.1 KB