• Imre Deak's avatar
    drm/i915/tc: Fix TypeC PHY connect/disconnect logic on ADL-P · 3e0abc76
    Imre Deak authored
    So far TC-cold was blocked only for the duration of TypeC mode resets.
    The DP-alt and legacy modes require TC-cold to be blocked also whenever
    the port is in use (AUX transfers, enable modeset), and this was ensured
    by the held PHY ownership flag. On ADL-P this doesn't work, since the
    PHY ownership flag is in a register backed by the PW#2 power well.
    Whenever this power well is disabled the ownership flag is cleared by
    the HW under the driver.
    
    The only way to cleanly release and re-acquire the PHY ownership flag
    and also allow for power saving (by disabling the display power wells
    and reaching DC5/6 states) is to hold the TC-cold blocking power domains
    while the PHY is connected and disconnect/reconnect the PHY on-demand
    around AUX transfers and modeset enable/disables. Let's do that,
    disconnecting a PHY with a 1 sec delay after it becomes idle. For
    consistency do this on all platforms and TypeC modes.
    
    v2: Add tc_mode!=disconnected and phy_is_owned asserts to
        __intel_tc_port_lock().
    
    Cc: José Roberto de Souza <jose.souza@intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-6-imre.deak@intel.com
    3e0abc76
intel_ddi.c 143 KB