• Shengjiu Wang's avatar
    ASoC: fsl_sai: MCLK bind with TX/RX enable bit · 3e4a8261
    Shengjiu Wang authored
    On i.MX8MP, the sai MCLK is bound with TX/RX enable bit,
    which means the TX/RE enable bit need to be enabled then
    MCLK can be output on PAD.
    
    Some codec (for example: WM8962) needs the MCLK output
    earlier, otherwise there will be issue for codec
    configuration.
    
    Add new soc data "mclk_with_tere" for this platform and
    enable the MCLK output in startup stage.
    
    As "mclk_with_tere" only applied to i.MX8MP, currently
    The soc data is shared with i.MX8MN, so need to add
    an i.MX8MN own soc data with "mclk_with_tere" disabled.
    
    Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com
    Link: https://lore.kernel.org/r/1683273322-2525-1-git-send-email-shengjiu.wang@nxp.com
    Signed-off-by: Mark Brown <broonie@kernel.org
    3e4a8261
fsl_sai.c 45.3 KB