• Jiadong.Zhu's avatar
    drm/amdgpu: MCBP based on DRM scheduler (v9) · 3f4c175d
    Jiadong.Zhu authored
    Trigger Mid-Command Buffer Preemption according to the priority of the software
    rings and the hw fence signalling condition.
    
    The muxer saves the locations of the indirect buffer frames from the software
    ring together with the fence sequence number in its fifo queue, and pops out
    those records when the fences are signalled. The locations are used to resubmit
    packages in preemption scenarios by coping the chunks from the software ring.
    
    v2: Update comment style.
    v3: Fix conflict caused by previous modifications.
    v4: Remove unnecessary prints.
    v5: Fix corner cases for resubmission cases.
    v6: Refactor functions for resubmission, calling fence_process in irq handler.
    v7: Solve conflict for removing amdgpu_sw_ring.c.
    v8: Add time threshold to judge if preemption request is needed.
    v9: Correct comment spelling. Set fence emit timestamp before rsu assignment.
    
    Cc: Christian Koenig <Christian.Koenig@amd.com>
    Cc: Luben Tuikov <Luben.Tuikov@amd.com>
    Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
    Cc: Michel Dänzer <michel@daenzer.net>
    Signed-off-by: default avatarJiadong.Zhu <Jiadong.Zhu@amd.com>
    Acked-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
    Acked-by: default avatarHuang Rui <ray.huang@amd.com>
    Acked-by: default avatarChristian König <christian.koenig@amd.com>
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    3f4c175d
amdgpu_ring.h 14.9 KB