azx_init_pci() always writes PCI config register ICH6_PCIREG_TCSEL
although this looks to be only defined on Intel systems and has a
different meaning on AMD systems. On AMD systems the PCI interrupt pin
control register is modified instead.

Since the meaning of offset 0x44 in device specific configuration space is
unknown for devices by other vendors, we only exclude AMD systems to
retain the current behaviour.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Takashi Iwai <tiwai@suse.de>