• Sarah Sharp's avatar
    xhci: Setup array of USB 2.0 and USB 3.0 ports. · da6699ce
    Sarah Sharp authored
    An xHCI host controller contains USB 2.0 and USB 3.0 ports, which can
    occur in any order in the PORTSC registers.  We cannot read the port speed
    bits in the PORTSC registers at init time to determine the port speed,
    since those bits are only valid when a USB device is plugged into the
    port.
    
    Instead, we read the "Supported Protocol Capability" registers in the xHC
    Extended Capabilities space.  Those describe the protocol, port offset in
    the PORTSC registers, and port count.  We use those registers to create
    two arrays of pointers to the PORTSC registers, one for USB 3.0 ports, and
    another for USB 2.0 ports.  A third array keeps track of the port protocol
    major revision, and is indexed with the internal xHCI port number.
    
    This commit is a bit big, but it should be queued for stable because the "Don't
    let the USB core disable SuperSpeed ports" patch depends on it.  There is no
    other way to determine which ports are SuperSpeed ports without this patch.
    Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
    Tested-by: default avatarDon Zickus <dzickus@redhat.com>
    Cc: stable@kernel.org
    da6699ce
xhci-mem.c 59.7 KB