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Amit Daniel Kachhap authored
AArch32 Instruction Set Attribute Register 6 (ID_ISAR6_EL1) and AArch32 Processor Feature Register 2 (ID_PFR2_EL1) identifies some new features for the Armv8 architecture. This registers will be utilized to add hwcaps for those cpu features. These registers are marked as reserved for Armv7 and should be a RAZ. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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