• Stephen Boyd's avatar
    Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner',... · cd8ca300
    Stephen Boyd authored
    Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next
    
     - S2RAM support for Marvell mvebu periph clks
    
    * clk-mvebu-periph-pm:
      clk: mvebu: armada-37xx-periph: add suspend/resume support
      clk: mvebu: armada-37xx-periph: save the IP base address in the driver data
    
    * clk-meson:
      clk: meson: meson8b: use the regmap in the internal reset controller
      clk: meson: meson8b: register the clock controller early
      clk: meson-axg: pcie: drop the mpll3 clock parent
      clk: meson: axg: round audio system master clocks down
      clk: meson: clk-pll: drop hard-coded rates from pll tables
      clk: meson: clk-pll: remove od parameters
      clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
      clk: meson: clk-pll: add enable bit
    
    * clk-allwinner:
      dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
      clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
      clk: sunxi-ng: a64: Add minimal rate for video PLLs
      clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
      clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
      clk: sunxi-ng: nkmp: Add constraint for maximum rate
      clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
      clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
      clk: sunxi-ng: Add maximum rate constraint to NM PLLs
      clk: sunxi-ng: h6: fix PWM gate/reset offset
      clk: sunxi-ng: h6: fix bus clocks' divider position
    
    * clk-mvebu-dup:
      clk: mvebu: ap806: Remove superfluous of_clk_add_provider
    
    * clk-davinci:
      clk: davinci: kill davinci_clk_reset_assert/deassert()
    cd8ca300
ap806-system-controller.c 5.09 KB