• Amit Cohen's avatar
    mlxsw: pci: Initialize page pool per CQ · 5642c6a0
    Amit Cohen authored
    Next patch will use page pool to allocate buffers for RDQ. Initialize
    page pool for each CQ, which is mapped 1:1 to RDQ. Page pool for each Rx
    queue enhances Rx side performance by reclaiming buffers back to each queue
    specific pool.
    
    When only one NAPI instance is the consumer of pages from page pool, it is
    recommended to pass it as part of 'page_pool_params', then page pool APIs
    will be done without special locks. mlxsw driver holds NAPI instance per
    CQ, so add page pool per CQ and use the existing NAPI instance.
    
    For now, pages are not allocated from the pool, next patch will use it.
    
    Some notes regarding 'page_pool_params':
    * Use PP_FLAG_DMA_MAP to allow page pool handles DMA mapping, for now
      do not use sync flag, as only the device writes to this memory and we
      read it only when it finishes writing there. This will probably be
      changed when we will support XDP.
    * Define 'order' according to maximum MTU and take into account software
      overhead. Some round up are done, which means that we allocate more pages
      than we really need. This can be improved later by using fragmented
      buffers.
    * Use pool_size = MLXSW_PCI_WQE_COUNT. This will be the size of 'ptr_ring',
      and should be the maximum amount of packets that page pool will allocate
      memory for. In our case, this is the queue size, defined as
      MLXSW_PCI_WQE_COUNT.
    Signed-off-by: default avatarAmit Cohen <amcohen@nvidia.com>
    Reviewed-by: default avatarPetr Machata <petrm@nvidia.com>
    Reviewed-by: default avatarIdo Schimmel <idosch@nvidia.com>
    Signed-off-by: default avatarPetr Machata <petrm@nvidia.com>
    Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
    Link: https://lore.kernel.org/r/02e5856ae7c572d4293ce6bb92c286ee6cfec800.1718709196.git.petrm@nvidia.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
    5642c6a0
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