Always disable L2 cache on PPC440GX.  All revs/speeds of silicon have
parity error problems despite errata claims to the contrary.
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>