• Tony Lindgren's avatar
    bus: ti-sysc: Flush posted write on enable and disable · 5ce8aee8
    Tony Lindgren authored
    Looks like we're missing flush of posted write after module enable and
    disable. I've seen occasional errors accessing various modules, and it
    is suspected that the lack of posted writes can also cause random reboots.
    
    The errors we can see are similar to the one below from spi for example:
    
    44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4CFG (Read): Data Access
    in User mode during Functional access
    ...
    mcspi_wait_for_reg_bit
    omap2_mcspi_transfer_one
    spi_transfer_one_message
    ...
    
    We also want to also flush posted write for disable. The clkctrl clock
    disable happens after module disable, and we don't want to have the
    module potentially stay active while we're trying to disable the clock.
    
    Fixes: d59b6056 ("bus: ti-sysc: Add generic enable/disable functions")
    Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    5ce8aee8
ti-sysc.c 73.7 KB