The C7xv-dsp on AM62A have 32KB L1 I-cache and a 64KB L1 D-cache. It
does not have an addressable l1dram . So, remove this optional sram
property from the bindings to fix device tree build warnings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240604171450.2455-1-hnagalla@ti.comSigned-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>