According to the datasheet, there are some registers can only be changed
when SHDN is 0.  Changing these settings during SHDN = 1 can compromise
device stability and performance specifications.

Saves SHDN before writing to these sensitive registers and restores SHDN
afterward.

Here is the register list codec driver of max98090 wants to change:
M98090_REG_QUICK_SYSTEM_CLOCK		0x04
M98090_REG_QUICK_SAMPLE_RATE		0x05
M98090_REG_DAI_INTERFACE		0x06
M98090_REG_DAC_PATH			0x07
M98090_REG_MIC_DIRECT_TO_ADC		0x08
M98090_REG_LINE_TO_ADC			0x09
M98090_REG_ANALOG_MIC_LOOP		0x0A
M98090_REG_ANALOG_LINE_LOOP		0x0B
M98090_REG_SYSTEM_CLOCK			0x1B
M98090_REG_CLOCK_MODE			0x1C
M98090_REG_CLOCK_RATIO_NI_MSB		0x1D
M98090_REG_CLOCK_RATIO_NI_LSB		0x1E
M98090_REG_CLOCK_RATIO_MI_MSB		0x1F
M98090_REG_CLOCK_RATIO_MI_LSB		0x20
M98090_REG_MASTER_MODE			0x21
M98090_REG_INTERFACE_FORMAT		0x22
M98090_REG_TDM_CONTROL			0x23
M98090_REG_TDM_FORMAT			0x24
M98090_REG_IO_CONFIGURATION		0x25
M98090_REG_FILTER_CONFIG		0x26
M98090_REG_INPUT_ENABLE			0x3E
M98090_REG_OUTPUT_ENABLE		0x3F
M98090_REG_BIAS_CONTROL			0x42
M98090_REG_DAC_CONTROL			0x43
M98090_REG_ADC_CONTROL			0x44
M98090_REG_DRC_TIMING			0x33
M98090_REG_DRC_COMPRESSOR		0x34
M98090_REG_DRC_EXPANDER			0x35
M98090_REG_DSP_FILTER_ENABLE		0x41
M98090_REG_EQUALIZER_BASE		0x46
M98090_REG_RECORD_BIQUAD_BASE		0xAF
M98090_REG_DIGITAL_MIC_ENABLE		0x13
M98090_REG_DIGITAL_MIC_CONFIG		0x14
Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20191128151908.180871-1-tzungbi@google.comSigned-off-by: Mark Brown <broonie@kernel.org>