• Thierry Reding's avatar
    clk: tegra: Model oscillator as clock · 63cc5a4d
    Thierry Reding authored
    Currently the Tegra clock driver simplifies the clock tree somewhat by
    taking advantage of the fact that clk_m runs at the same frequency as
    the oscillator. While that's true on all currently supported SoCs, it
    does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
    divided down from the oscillator frequency. To support that setup, add
    a separate clock for the oscillator that both clk_m and pll_ref derive
    from.
    
    Modify the tegra_osc_clk_init() function to take an additional divider
    parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
    will read the divider from a register in the clock & reset controller.
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    63cc5a4d
clk.h 19.4 KB