• Haren Myneni's avatar
    crypto/nx: Initialize 842 high and normal RxFIFO control registers · 656ecc16
    Haren Myneni authored
    NX increments readOffset by FIFO size in receive FIFO control register
    when CRB is read. But the index in RxFIFO has to match with the
    corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
    may be processing incorrect CRBs and can cause CRB timeout.
    
    VAS FIFO offset is 0 when the receive window is opened during
    initialization. When the module is reloaded or in kexec boot, readOffset
    in FIFO control register may not match with VAS entry. This patch adds
    nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
    control register for both high and normal FIFOs.
    Signed-off-by: default avatarHaren Myneni <haren@us.ibm.com>
    [mpe: Fixup uninitialized variable warning]
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    656ecc16
opal-api.h 29.4 KB