The Meson Timer IP has two clock inputs:
- pclk which is used as "system clock" timebase of Timer E
- xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer
  A, B, C, D and E

The IP block has four internal dividers (XTAL is running at 24MHz):
- "xtal div 24" for 1us resolution
- "xtal div 240" for 10us resolution
- "xtal div 2400" for 100us resolution
- "xtal div 24000" for 1ms resolution
Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>