• Kenji Kaneshige's avatar
    [IA64] Fix irq migration in multiple vector domain · a6cd6322
    Kenji Kaneshige authored
    Fix the problem that the following error message is sometimes displayed
    at irq migration when vector domain is enabled.
    
        "Unexpected interrupt vector %d on CPU %d is not mapped to any IRQ!"
    
    The cause of this problem is an interrupt is sent to the previous
    target CPU after cleaning up vector to irq mapping table. To clean up
    vector to irq map on the previous target CPU safty, change the irq
    migration in multiple vector domain as follows. The original idea is
    from x86 interrupt management code.
    
        - Delay vector to irq table cleanup until the interrupts are sent
          to new target CPUs. By this, it is ensured that target CPU is
          completely changed on the interrupt controller side.
    
        - Even after the interrupts are sent to new target CPUs, there can
          be pended interrupts remaining on the previous target CPU. So we
          need to delay clearning up vector to irq table until the pended
          interrupt is handled. For this, send IPI to the previous target
          CPU with lower priority vector and clean up vector to irq table
          in its handler.
    
    This patch affects only to irq migration code with multiple vector
    domain is enabled.
    Signed-off-by: default avatarKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
    Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
    a6cd6322
msi_ia64.c 3.68 KB