• Matt Roper's avatar
    drm/i915/xehp: Create separate reg definitions for new MCR registers · 77fa9efc
    Matt Roper authored
    Starting in Xe_HP, several registers our driver works with have been
    converted from singleton registers into replicated registers with
    multicast behavior.  Although the registers are still located at the
    same MMIO offsets as on previous platforms, let's duplicate the register
    definitions in preparation for upcoming patches that will handle
    multicast registers in a special manner.
    
    The registers that are now replicated on Xe_HP are:
     * PAT_INDEX (mslice replication)
     * FF_MODE2 (gslice replication)
     * COMMON_SLICE_CHICKEN3 (gslice replication)
     * SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
     * SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
     * LNCFCMOCS (lncf replication)
    
    Note that there are a couple places in selftest_mocs.c where the
    gen9 version of LNCFCMOCS is still used without regards for which
    platform we're on.  Those cases are just doing an offset lookup and not
    issuing any CPU reads/writes of the register, so the potentially
    multicast nature of the register doesn't come into play.
    
    v2:
     - Add commit message note about the unconditional GEN9_LNCFCMOCS usage
       in selftest_mocs.  (Bala)
     - Include some additional TLB registers.
    
    Bspec: 66534
    Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
    Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
    Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-3-matthew.d.roper@intel.com
    77fa9efc
intel_gtt.c 18 KB