Previously it was not possible to achieve clock rates of 24.576MHz and
22.5792MHz, which are commonly required core clocks for the i2s
peripheral of v3s based SoCs.

Add support for those clock rates through the audio pll's sigma-delta
modulator.
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210218112001.479018-2-t.schramm@manjaro.org