• Sean Christopherson's avatar
    KVM: x86/mmu: Optimize and clean up so called "last nonleaf level" logic · 7cd138db
    Sean Christopherson authored
    Drop the pre-computed last_nonleaf_level, which is arguably wrong and at
    best confusing.  Per the comment:
    
      Can have large pages at levels 2..last_nonleaf_level-1.
    
    the intent of the variable would appear to be to track what levels can
    _legally_ have large pages, but that intent doesn't align with reality.
    The computed value will be wrong for 5-level paging, or if 1gb pages are
    not supported.
    
    The flawed code is not a problem in practice, because except for 32-bit
    PSE paging, bit 7 is reserved if large pages aren't supported at the
    level.  Take advantage of this invariant and simply omit the level magic
    math for 64-bit page tables (including PAE).
    
    For 32-bit paging (non-PAE), the adjustments are needed purely because
    bit 7 is ignored if PSE=0.  Retain that logic as is, but make
    is_last_gpte() unique per PTTYPE so that the PSE check is avoided for
    PAE and EPT paging.  In the spirit of avoiding branches, bump the "last
    nonleaf level" for 32-bit PSE paging by adding the PSE bit itself.
    
    Note, bit 7 is ignored or has other meaning in CR3/EPTP, but despite
    FNAME(walk_addr_generic) briefly grabbing CR3/EPTP in "pte", they are
    not PTEs and will blow up all the other gpte helpers.
    Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
    Message-Id: <20210622175739.3610207-51-seanjc@google.com>
    Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    7cd138db
paging_tmpl.h 33.2 KB