• Hari Nagalla's avatar
    arm64: dts: ti: k3-j784s4-main: Add R5F cluster nodes · 7e5fd896
    Hari Nagalla authored
    The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS)
    subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
    the MCU domain, and the remaining three clusters are present in the
    MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality
    of the R5FSS is same as the R5FSS functionality on earlier K3 platform
    device J721S2. Each of the R5FSS can be configured at boot time to be
    either run in a LockStep mode or in an Asymmetric Multi Processing (AMP)
    fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled
    Memory (TCM) internal memories for each core split between two banks -
    ATCM and BTCM (further interleaved into two banks). There are some IP
    integration differences from standard Arm R5 clusters such as the absence
    of an ACP port, presence of an additional TI-specific Region Address
    Translater (RAT) module for translating 32-bit CPU addresses into
    larger system bus addresses etc.
    
    Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are
    each added as child nodes to the corresponding cluster node. The clusters
    are configured to run in LockStep mode by default, with the ATCMs enabled
    to allow the R5 cores to execute code from DDR with boot-strapping code
    from ATCM. The inter-processor communication between the main A72 cores
    and these processors is achieved through shared memory and Mailboxes.
    
    The following firmware names are used by default for these cores, and
    can be overridden in a board dts file if needed:
        MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes)
        MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode)
        MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes)
        MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode)
        MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes)
        MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode)
        MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode)
        MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode)
    Signed-off-by: default avatarHari Nagalla <hnagalla@ti.com>
    Link: https://lore.kernel.org/r/20230502231527.25879-2-hnagalla@ti.comSigned-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
    7e5fd896
k3-j784s4-mcu-wakeup.dtsi 10.4 KB