All MStar v7 SoCs have an internal SRAM region that is between 64KB
(infinity2m) and 128KB(infinity3, mercury5).

The region is always at the same base address and is used for the
second stage loader (MStar IPL or u-boot SPL) and will be used for
the DDR self-refresh entry code within the kernel eventually.

This patch adds a 128KB region to the SoC and the minimum 64KB SRAM
region to the base dtsi. Families with more SRAM will override the
size in their family level dtsi.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>