• Dmitry Osipenko's avatar
    memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interrupt · adbcec88
    Dmitry Osipenko authored
    The memory clock-rate change could be running on a non-boot CPU, while the
    boot CPU handles the EMC interrupt. This introduces an unnecessary latency
    since boot CPU should handle the interrupt and then notify the sibling CPU
    about clock-rate change completion. In some rare cases boot CPU could be
    in uninterruptible state for a significant time (like in a case of KASAN +
    NFS root), it could get to the point that completion timeouts before boot
    CPU gets a chance to handle interrupt. The solution is to get rid of the
    completion and replace it with interrupt-status polling.
    Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    adbcec88
tegra20-emc.c 17 KB