• Joseph Lo's avatar
    memory: tegra: Add EMC scaling support code for Tegra210 · 10de2114
    Joseph Lo authored
    This is the initial patch for Tegra210 EMC frequency scaling. It has the
    code to program various aspects of the EMC that are standardized, but it
    does not yet include the specific programming sequence needed for clock
    scaling.
    
    The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4
    need to perform training of the RAM before it can be used. Firmware will
    perform this training during early boot and pass a table of supported
    frequencies to the kernel via device tree.
    
    For the frequencies above 800 MHz, periodic retraining is needed to
    compensate for changes in timing. This periodic training will have to be
    performed until the frequency drops back to or below 800 MHz.
    
    This driver provides helpers used during this runtime retraining that
    will be used by the sequence specific code in a follow-up patch.
    
    Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>.
    Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    10de2114
tegra210-mc.h 1.85 KB