• Lukas Wunner's avatar
    PCI: pciehp: Assume NoCompl+ for Thunderbolt ports · 493fb50e
    Lukas Wunner authored
    Certain Thunderbolt 1 controllers claim to support Command Completed events
    (value of 0b in the No Command Completed Support field of the Slot
    Capabilities register) but in reality they neither set the Command
    Completed bit in the Slot Status register nor signal a Command Completed
    interrupt:
    
      8086:1513  CV82524  [Light Ridge 4C  2010]
      8086:151a  DSL2310  [Eagle Ridge 2C  2011]
      8086:151b  CVL2510  [Light Peak 2C   2010]
      8086:1547  DSL3510  [Cactus Ridge 4C 2012]
      8086:1548  DSL3310  [Cactus Ridge 2C 2012]
      8086:1549  DSL2210  [Port Ridge 1C   2011]
    
    All known newer chips (Redwood Ridge and onwards) set No Command Completed
    Support, indicating that they do not support Command Completed events.
    
    The user-visible impact is that after unplugging such a device, 2 seconds
    elapse until pciehp is unbound.  That's because on ->remove,
    pcie_write_cmd() is called via pcie_disable_notification() and every call
    to pcie_write_cmd() takes 2 seconds (1 second for each invocation of
    pcie_wait_cmd()):
    
      [  337.942727] pciehp 0000:0a:00.0:pcie204: Timeout on hotplug command 0x1038 (issued 21176 msec ago)
      [  340.014735] pciehp 0000:0a:00.0:pcie204: Timeout on hotplug command 0x0000 (issued 2072 msec ago)
    
    That by itself has always been unpleasant, but the situation has become
    worse with commit cc27b735 ("PCI/portdrv: Turn off PCIe services during
    shutdown"):  Now pciehp is unbound on ->shutdown.  Because Thunderbolt
    controllers typically have 4 hotplug ports, every reboot and shutdown is
    now delayed by 8 seconds, plus another 2 seconds for every attached
    Thunderbolt 1 device.
    
    Thunderbolt hotplug slots are not physical slots that one inserts cards
    into, but rather logical hotplug slots implemented in silicon.  Devices
    appear beyond those logical slots once a PCI tunnel is established on top
    of the Thunderbolt Converged I/O switch.  One would expect commands written
    to the Slot Control register to be executed immediately by the silicon, so
    for simplicity we always assume NoCompl+ for Thunderbolt ports.
    
    Fixes: cc27b735 ("PCI/portdrv: Turn off PCIe services during shutdown")
    Tested-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
    Signed-off-by: default avatarLukas Wunner <lukas@wunner.de>
    Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
    Cc: stable@vger.kernel.org	# v4.12+
    Cc: Sinan Kaya <okaya@codeaurora.org>
    Cc: Yehezkel Bernat <yehezkel.bernat@intel.com>
    Cc: Michael Jamet <michael.jamet@intel.com>
    Cc: Andreas Noever <andreas.noever@gmail.com>
    493fb50e
pciehp_hpc.c 24 KB