On newer chipsets, SPI controller has fifos of larger size.
So add the fifo size bit mask entry in SoC specific data structure.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Link: https://lore.kernel.org/r/a0889abf17a9fbc7077f10be0f0342b7ebdf9361.1594957019.git.eswara.kota@linux.intel.comSigned-off-by: Mark Brown <broonie@kernel.org>