• Lorenzo Pieralisi's avatar
    irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing · 3a0fff0f
    Lorenzo Pieralisi authored
    The GIC architecture specification defines a set of registers
    for redistributors and ITSes that control the sharebility and
    cacheability attributes of redistributors/ITSes initiator ports
    on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER,
    GITS_BASER<n>).
    
    Architecturally the GIC provides a means to drive shareability
    and cacheability attributes signals and related IWB/OWB/ISH barriers
    but it is not mandatory for designs to wire up the corresponding
    interconnect signals that control the cacheability/shareability
    of transactions.
    
    Redistributors and ITSes interconnect ports can be connected to
    non-coherent interconnects that are not able to manage the
    shareability/cacheability attributes; this implicitly makes
    the redistributors and ITSes non-coherent observers.
    
    So far, the GIC driver on probe executes a write to "probe" for
    the redistributors and ITSes registers shareability bitfields
    by writing a value (ie InnerShareable - the sh...
    3a0fff0f
irq-gic-v3.c 66 KB