• Mark Rutland's avatar
    arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap · 8bf0a804
    Mark Rutland authored
    When Priority Mask Hint Enable (PMHE) == 0b1, the GIC may use the PMR
    value to determine whether to signal an IRQ to a PE, and consequently
    after a change to the PMR value, a DSB SY may be required to ensure that
    interrupts are signalled to a CPU in finite time. When PMHE == 0b0,
    interrupts are always signalled to the relevant PE, and all masking
    occurs locally, without requiring a DSB SY.
    
    Since commit:
    
      f2266504 ("arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear")
    
    ... we handle this dynamically: in most cases a static key is used to
    determine whether to issue a DSB SY, but the entry code must read from
    ICC_CTLR_EL1 as static keys aren't accessible from plain assembly.
    
    It would be much nicer to use an alternative instruction sequence for
    the DSB, as this would avoid the need to read from ICC_CTLR_EL1 in the
    entry code, and for most other code this will result in simpler code
    generation with fewer instructions and fewer branches.
    
    This patch adds a new ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap which is
    only set when ICC_CTLR_EL1.PMHE == 0b0 (and GIC priority masking is in
    use). This allows us to replace the existing users of the
    `gic_pmr_sync` static key with alternative sequences which default to a
    DSB SY and are relaxed to a NOP when PMHE is not in use.
    
    The entry assembly management of the PMR is slightly restructured to use
    a branch (rather than multiple NOPs) when priority masking is not in
    use. This is more in keeping with other alternatives in the entry
    assembly, and permits the use of a separate alternatives for the
    PMHE-dependent DSB SY (and removal of the conditional branch this
    currently requires). For consistency I've adjusted both the save and
    restore paths.
    
    According to bloat-o-meter, when building defconfig +
    CONFIG_ARM64_PSEUDO_NMI=y this shrinks the kernel text by ~4KiB:
    
    | add/remove: 4/2 grow/shrink: 42/310 up/down: 332/-5032 (-4700)
    
    The resulting vmlinux is ~66KiB smaller, though the resulting Image size
    is unchanged due to padding and alignment:
    
    | [mark@lakrids:~/src/linux]% ls -al vmlinux-*
    | -rwxr-xr-x 1 mark mark 137508344 Jan 17 14:11 vmlinux-after
    | -rwxr-xr-x 1 mark mark 137575440 Jan 17 13:49 vmlinux-before
    | [mark@lakrids:~/src/linux]% ls -al Image-*
    | -rw-r--r-- 1 mark mark 38777344 Jan 17 14:11 Image-after
    | -rw-r--r-- 1 mark mark 38777344 Jan 17 13:49 Image-before
    
    Prior to this patch we did not verify the state of ICC_CTLR_EL1.PMHE on
    secondary CPUs. As of this patch this is verified by the cpufeature code
    when using GIC priority masking (i.e. when using pseudo-NMIs).
    
    Note that since commit:
    
      7e3a57fa ("arm64: Document ICC_CTLR_EL3.PMHE setting requirements")
    
    ... Documentation/arm64/booting.rst specifies:
    
    |      - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
    |        all CPUs the kernel is executing on, and must stay constant
    |        for the lifetime of the kernel.
    
    ... so that should not adversely affect any compliant systems, and as
    we'll only check for the absense of PMHE when using pseudo-NMIs, this
    will only fire when such mismatch will adversely affect the system.
    Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
    Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
    Cc: Mark Brown <broonie@kernel.org>
    Cc: Will Deacon <will@kernel.org>
    Link: https://lore.kernel.org/r/20230130145429.903791-5-mark.rutland@arm.comSigned-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    8bf0a804
cpufeature.c 121 KB