• Lionel Landwerlin's avatar
    drm/i915: store all subslice masks · 8cc76693
    Lionel Landwerlin authored
    Up to now, subslice mask was assumed to be uniform across slices. But
    starting with Cannonlake, slices can be asymmetric (for example slice0
    has different number of subslices as slice1+). This change stores all
    subslices masks for all slices rather than having a single mask that
    applies to all slices.
    
    v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
        Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
        Readability changes (Tvrtko)
        Add EU index helper (Tvrtko)
    
    v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko)
        Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko)
        Reformat debug prints for subslices (Tvrtko)
    
    v4: Change eu_mask helper into sseu_set_eus() (Tvrtko)
    
    v5: With Haswell reporting masks & counts, bump sseu_*_eus() functions
        to use u16 (Lionel)
    
    v6: Fix sseu_get_eus() for > 8 EUs per subslice (Lionel)
    
    v7: Change debugfs enabels for number of subslices per slice, will
        need a small igt/pm_sseu change (Lionel)
        Drop subslice_total field from sseu_dev_info, rely on
        sseu_subslice_total() to recompute the value instead (Lionel)
    
    v8: Remove unused function compute_subslice_total() (Lionel)
    Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
    Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-2-lionel.g.landwerlin@intel.com
    8cc76693
intel_lrc.c 77.3 KB