• Tsukasa OI's avatar
    RISC-V: clarify the QEMU workaround in ISA parser · 8f501be8
    Tsukasa OI authored
    
    
    Extensions prefixed with "Su" won't corrupt the workaround in many
    cases.  The only exception is when the first multi-letter extension in the
    ISA string begins with "Su" and is not prefixed with an underscore.
    
    For instance, following ISA string can confuse this QEMU workaround.
    
    *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
    
    However, this case is very unlikely because extensions prefixed by either
    "Z", "Sm" or "Ss" will most likely precede first.
    
    For instance, the "Suclic" extension (draft as of now) will be placed after
    related "Smclic" and "Ssclic" extensions.  It's also highly likely that
    other unprivileged extensions like "Zba" will precede.
    
    It's also possible to suppress the issue in the QEMU workaround with an
    underscore.  Following ISA string won't confuse the QEMU workaround.
    
    *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
    
    This fix is to tell kernel developers the nature of this workaround
    precisely.  There are some "Su*" extensions to be ratified but don't worry
    about this workaround too much.
    
    This commit comes with other minor editorial fixes (for minor wording and
    spacing issues, without changing the meaning).
    Signed-off-by: default avatarTsukasa OI <research_trasio@irq.a4lg.com>
    Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
    Link: https://lore.kernel.org/r/8a127608cf6194a6d288289f2520bd1744b81437.1690350252.git.research_trasio@irq.a4lg.com
    
    Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
    8f501be8
cpufeature.c 20.8 KB