The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
uses these as source clocks for some of its RCGs to generate clocks that
finally feed to the DSI host controller.

Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to
the DSI host. Use the DSI PHY provided clocks to set up the parents
of these assigned clocks.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>