• Vivek Gautam's avatar
    iommu/io-pgtable-arm: Add support to use system cache · 90ec7a76
    Vivek Gautam authored
    Few Qualcomm platforms such as, sdm845 have an additional outer
    cache called as System cache, aka. Last level cache (LLC) that
    allows non-coherent devices to upgrade to using caching.
    This cache sits right before the DDR, and is tightly coupled
    with the memory controller. The clients using this cache request
    their slices from this system cache, make it active, and can then
    start using it.
    
    There is a fundamental assumption that non-coherent devices can't
    access caches. This change adds an exception where they *can* use
    some level of cache despite still being non-coherent overall.
    The coherent devices that use cacheable memory, and CPU make use of
    this system cache by default.
    
    Looking at memory types, we have following -
    a) Normal uncached :- MAIR 0x44, inner non-cacheable,
                          outer non-cacheable;
    b) Normal cached :-   MAIR 0xff, inner read write-back non-transient,
                          outer read write-back non-transient;
                          attribute setting for coherenet I/O devices.
    and, for non-coherent i/o devices that can allocate in system cache
    another type gets added -
    c) Normal sys-cached :- MAIR 0xf4, inner non-cacheable,
                            outer read write-back non-transient
    
    Coherent I/O devices use system cache by marking the memory as
    normal cached.
    Non-coherent I/O devices should mark the memory as normal
    sys-cached in page tables to use system cache.
    Acked-by: default avatarRobin Murphy <robin.murphy@arm.com>
    Signed-off-by: default avatarVivek Gautam <vivek.gautam@codeaurora.org>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    90ec7a76
io-pgtable-arm.c 32.9 KB