• Yasha Cherikovsky's avatar
    MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions · 932afdee
    Yasha Cherikovsky authored
    MIPSR6 CPUs do not support unaligned load/store instructions
    (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
    
    Currently the MIPS tree has some special cases to avoid these
    instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
    
    This patch declares a new Kconfig variable:
    CONFIG_CPU_HAS_LOAD_STORE_LR.
    This variable indicates that the CPU supports these instructions.
    
    Then, the patch does the following:
    - Carefully selects this option on all CPUs except MIPSR6.
    - Switches all the special cases to test for the new variable,
      and inverts the logic:
        '#ifndef CONFIG_CPU_MIPSR6' turns into
        '#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
        and vice-versa.
    
    Also, when this variable is NOT selected (e.g. MIPSR6),
    CONFIG_GENERIC_CSUM will default to 'y', to compile generic
    C checksum code (instead of special assembly code that uses the
    unsupported instructions).
    
    This commit should not affect any existing CPU, and is required
    for future Lexra CPU support, that misses these instructions too.
    Signed-off-by: default avatarYasha Cherikovsky <yasha.che3@gmail.com>
    Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
    Patchwork: https://patchwork.linux-mips.org/patch/20808/
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: Paul Burton <paul.burton@mips.com>
    Cc: James Hogan <jhogan@kernel.org>
    Cc: linux-mips@linux-mips.org
    Cc: linux-kernel@vger.kernel.org
    932afdee
unaligned.c 61.3 KB