• Hersen Wu's avatar
    drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2) · 9340dfd3
    Hersen Wu authored
     This interface is for dGPU Navi1x. Linux dc-pplib interface depends
     on window driver dc implementation.
    
     For Navi1x, clock settings of dcn watermarks are fixed. the settings
     should be passed to smu during boot up and resume from s3.
     boot up: dc calculate dcn watermark clock settings within dc_create,
     dcn20_resource_construct, then call pplib functions below to pass
     the settings to smu:
     smu_set_watermarks_for_clock_ranges
     smu_set_watermarks_table
     navi10_set_watermarks_table
     smu_write_watermarks_table
    
     For Renoir, clock settings of dcn watermark are also fixed values.
     dc has implemented different flow for window driver:
     dc_hardware_init / dc_set_power_state
     dcn10_init_hw
     notify_wm_ranges
     set_wm_ranges
    
     For Linux
     smu_set_watermarks_for_clock_ranges
     renoir_set_watermarks_table
     smu_write_watermarks_table
    
     dc_hardware_init -> amdgpu_dm_init
     dc_set_power_state --> dm_resume
    
     therefore, linux dc-pplib interface of navi10/12/14 is different
     from that of Renoir.
    
    v2: add missing unlock in error case
    Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
    Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    9340dfd3
amdgpu_dm.c 240 KB