• Gautham R. Shenoy's avatar
    powerpc/smp: Add support detecting thread-groups sharing L2 cache · 9538abee
    Gautham R. Shenoy authored
    On POWER systems, groups of threads within a core sharing the L2-cache
    can be indicated by the "ibm,thread-groups" property array with the
    identifier "2".
    
    This patch adds support for detecting this, and when present, populate
    the populating the cpu_l2_cache_mask of every CPU to the core-siblings
    which share L2 with the CPU as specified in the by the
    "ibm,thread-groups" property array.
    
    On a platform with the following "ibm,thread-group" configuration
    		 00000001 00000002 00000004 00000000
    		 00000002 00000004 00000006 00000001
    		 00000003 00000005 00000007 00000002
    		 00000002 00000004 00000000 00000002
    		 00000004 00000006 00000001 00000003
    		 00000005 00000007
    
    Without this patch, the sched-domain hierarchy for CPUs 0,1 would be
    	CPU0 attaching sched-domain(s):
    	domain-0: span=0,2,4,6 level=SMT
    	domain-1: span=0-7 level=CACHE
    	domain-2: span=0-15,24-39,48-55 level=MC
    	domain-3: span=0-55 level=DIE
    
    	CPU1 attaching sched-domain(s):
    	domain-0: span=1,3,5,7 level=SMT
    	domain-1: span=0-7 level=CACHE
    	domain-2: span=0-15,24-39,48-55 level=MC
    	domain-3: span=0-55 level=DIE
    
    The CACHE domain at 0-7 is incorrect since the ibm,thread-groups
    sub-array
    [00000002 00000002 00000004
     00000000 00000002 00000004 00000006
     00000001 00000003 00000005 00000007]
    indicates that L2 (Property "2") is shared only between the threads of a single
    group. There are "2" groups of threads where each group contains "4"
    threads each. The groups being {0,2,4,6} and {1,3,5,7}.
    
    With this patch, the sched-domain hierarchy for CPUs 0,1 would be
         	CPU0 attaching sched-domain(s):
    	domain-0: span=0,2,4,6 level=SMT
    	domain-1: span=0-15,24-39,48-55 level=MC
    	domain-2: span=0-55 level=DIE
    
    	CPU1 attaching sched-domain(s):
    	domain-0: span=1,3,5,7 level=SMT
    	domain-1: span=0-15,24-39,48-55 level=MC
    	domain-2: span=0-55 level=DIE
    
    The CACHE domain with span=0,2,4,6 for CPU 0 (span=1,3,5,7 for CPU 1
    resp.) gets degenerated into the SMT domain. Furthermore, the
    last-level-cache domain gets correctly set to the SMT sched-domain.
    Signed-off-by: default avatarGautham R. Shenoy <ego@linux.vnet.ibm.com>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/1607596739-32439-5-git-send-email-ego@linux.vnet.ibm.com
    9538abee
smp.h 7.17 KB