• Paul Walmsley's avatar
    [ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding · 95f538ac
    Paul Walmsley authored
    The DPLL FREQSEL jitter correction bits are set based on a table in
    the 34xx TRM, Table 4-38, according to the DPLL's internal clock
    frequency "Fint."  Several Fint frequency ranges are missing from this
    table.  Previously, we allowed these Fint frequency ranges to be
    selected in the rate rounding code, but did not change the FREQSEL bits.
    Correspondence with the OMAP hardware team indicates that Fint values
    not in the table should not be used.  So, prevent them from being
    selected during DPLL rate rounding.  This removes warnings and also
    can prevent the chip from locking up.
    
    The first pass through the rate rounding code will update the DPLL max
    and min dividers appropriately, so later rate rounding passes will run
    faster than the first.
    
    Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several
    test cycles of this patch - thanks Peter.
    
    linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9.
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    Cc: Peter de Schrijver <peter.de-schrijver@nokia.com>
    Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    95f538ac
clock.c 26.9 KB