• Nandor Han's avatar
    serial: imx-serial - update UART IMX driver to use cyclic DMA · 9d297239
    Nandor Han authored
    The IMX UART has a 32 bytes HW buffer which can be filled up in
    2777us at 115200 baud or 80us at 4Mbaud (supported by IMX53).
    Taking this in consideration there is a good probability to lose
    data because of the DMA startup latency.
    Our tests (explained below) indicates a latency up to 4400us when
    creating interrupt load and ~70us without. When creating interrupt
    load I was able to see continuous overrun errors by checking serial
    driver statistics using the command:
    `cat /proc/tty/driver/IMX-uart`.
    
    Replace manual restart of DMA with cyclic DMA to eliminate data loss
    due to DMA engine startup latency (similar approch to atmel_serial.c
    driver). As result the DMA engine will start on the first serial data
    transfer and stops only when serial port is closed.
    
    Tests environment:
     Using the m53evk board I have used a GPIO for profiling the IMX
     serial driver.
      - The RX line and GPIO were connected to oscilloscope.
      - Run a small test program on the m53evk board that will only open
        and read data from ttymxc2 port.
      - Connect the ttymxc2 port to my laptop using a USB serial converter
        where another test program is running, able to send configurable
        packet lengths and intervals.
      - Serial ports configured at 115200 8N1.
      - Interrupts load created by disconnecting/connecting (3s interval)
        a USB hub, using a digital switch, with 4 USB devices (USB-Serial
        converter, USB SD card, etc) connected.
        (around 160 interrupts/second generated)
      - The GPIO was toggled HI in the `imx_int` when USR1_RRDY or USR1_AGTIM
        events are received and toggled back, once the DMA configuration
        is finalized, at the end of `imx_dma_rxint`.
    
    Measurements:
    The measurements were done from the end of the last byte (RX line) until
    the GPIO was toggled back LOW.
    
    Note: The GPIO toggling was done using `gpiod_set_value` method.
    
    Tests performed:
       1. Sending 9 bytes packets at 8ms interval. Having the 9 bytes packets
          will activate the RRDY threshold event and IMX serial interrupt
          called.
          Results:
            - DMA start latency (interrupt start latency +
               DMA configuration) consistently 70us when system not loaded.
            - DMA start latency up to 4400us when system loaded.
       2. Sending 40 bytes packet at 8mS interval.
          Results with load:
            - Able to observe overruns by running:
               `watch -n1 cat /proc/tty/driver/IMX-uart`
    Tested-by: default avatarPeter Senna Tschudin <peter.senna@collabora.com>
    Acked-by: default avatarPeter Senna Tschudin <peter.senna@collabora.com>
    Signed-off-by: default avatarNandor Han <nandor.han@ge.com>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    9d297239
imx.c 60.4 KB