• Fenghua Yu's avatar
    x86/umwait: Initialize umwait control values · bd688c69
    Fenghua Yu authored
    umwait or tpause allows the processor to enter a light-weight
    power/performance optimized state (C0.1 state) or an improved
    power/performance optimized state (C0.2 state) for a period specified by
    the instruction or until the system time limit or until a store to the
    monitored address range in umwait.
    
    IA32_UMWAIT_CONTROL MSR register allows the OS to enable/disable C0.2 on
    the processor and to set the maximum time the processor can reside in C0.1
    or C0.2.
    
    By default C0.2 is enabled so the user wait instructions can enter the
    C0.2 state to save more power with slower wakeup time.
    
    Andy Lutomirski proposed to set the maximum umwait time to 100000 cycles by
    default. A quote from Andy:
    
      "What I want to avoid is the case where it works dramatically differently
       on NO_HZ_FULL systems as compared to everything else. Also, UMWAIT may
       behave a bit differently if the max timeout is hit, and I'd like that
       path to get exercised widely by making it happen even on default
       configs."
    
    A sysfs interface to adjust the time and the C0.2 enablement is provided in
    a follow up change.
    
    [ tglx: Renamed MSR_IA32_UMWAIT_CONTROL_MAX_TIME to
      	MSR_IA32_UMWAIT_CONTROL_TIME_MASK because the constant is used as
      	mask throughout the code.
    	Massaged comments and changelog ]
    Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
    Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    Reviewed-by: default avatarAshok Raj <ashok.raj@intel.com>
    Reviewed-by: default avatarAndy Lutomirski <luto@kernel.org>
    Cc: "Borislav Petkov" <bp@alien8.de>
    Cc: "H Peter Anvin" <hpa@zytor.com>
    Cc: "Peter Zijlstra" <peterz@infradead.org>
    Cc: "Tony Luck" <tony.luck@intel.com>
    Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
    Link: https://lkml.kernel.org/r/1560994438-235698-3-git-send-email-fenghua.yu@intel.com
    bd688c69
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