• Quanyang Wang's avatar
    drm: xlnx: zynqmp_dpsub: Call pm_runtime_get_sync before setting pixel clock · a19effb6
    Quanyang Wang authored
    The Runtime PM subsystem will force the device "fd4a0000.zynqmp-display"
    to enter suspend state while booting if the following conditions are met:
    - the usage counter is zero (pm_runtime_get_sync hasn't been called yet)
    - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node)
    - no other device in the same power domain (dpdma node has no
    		"power-domains = <&zynqmp_firmware PD_DP>" property)
    
    So there is a scenario as below:
    1) DP device enters suspend state   <- call zynqmp_gpd_power_off
    2) zynqmp_disp_crtc_setup_clock	    <- configurate register VPLL_FRAC_CFG
    3) pm_runtime_get_sync		    <- call zynqmp_gpd_power_on and clear previous
    				       VPLL_FRAC_CFG configuration
    4) clk_prepare_enable(disp->pclk)   <- enable failed since VPLL_FRAC_CFG
    				       configuration is corrupted
    
    From above, we can see that pm_runtime_get_sync may clear register
    VPLL_FRAC_CFG configuration and result the failure of clk enabling.
    Putting pm_runtime_get_sync at the very beginning of the function
    zynqmp_disp_crtc_atomic_enable can resolve this issue.
    Signed-off-by: default avatarQuanyang Wang <quanyang.wang@windriver.com>
    Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
    Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
    a19effb6
zynqmp_disp.c 45.8 KB