1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex
   mode. Which the MAC processor generates CRS/COL by itself instead of
   receive it from PHY processor.

2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the
   MAC processor working right while calculating IPv6 RSS in 10/100
   mode.

3. Group the workaround codes all together.
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>