• Vignesh Raghavendra's avatar
    arm64: dts: ti: Introduce AM62A7 family of SoCs · 5fc6b1b6
    Vignesh Raghavendra authored
    The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
    can run edge AI applications with Video/Vision processing. This provides
    advanced system integration with high security support to enable a broad
    set of applications in industrial/automotive markets such as, driver
    monitoring, machine vision, smart camera, eMirror, front camera,
    robotics, and building automation.
    
    Some highlights of AM62A SoC are:
    * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
      core variants are provided in the same package to allow HW compatible
      designs.
    * One Device manager Cortex-R5F for system power and resource management, and
      one Cortex-R5F for Functional Safety or general-purpose usage.
    * One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
      accelerator (MMA) for Deep Learning usage.
    * VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
      315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
      and vision image processing.
    * H.264/H.265 Video Encode/Decode. + Motion JPEG encode
    * Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
      clock support for 2K display resolution.
    * Integrated Giga-bit Ethernet switch supporting up to a total of two external
      ports (TSN capable).
    * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
      connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
      Camera, eCAP/eQEP, ePWM, among other peripherals.
    * Dedicated Centralized Hardware Security Module with support for secure boot,
      debug security and crypto acceleration and trusted execution environment
    * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
    * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
      battery powered system design.
    
    More details about the SoCs can be found in the Technical Reference Manual:
    https://www.ti.com/lit/zip/spruj16Co-developed-by: default avatarBryan Brattlof <bb@ti.com>
    Signed-off-by: default avatarBryan Brattlof <bb@ti.com>
    Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
    Tested-by: default avatarDevarsh Thakkar <devarsht@ti.com>
    Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
    5fc6b1b6
k3-am62a-mcu.dtsi 1.06 KB
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM625 SoC Family MCU Domain peripherals
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu {
	mcu_pmx0: pinctrl@4084000 {
		compatible = "pinctrl-single";
		reg = <0x00 0x04084000 0x00 0x88>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
		status = "disabled";
	};

	mcu_uart0: serial@4a00000 {
		compatible = "ti,am64-uart", "ti,am654-uart";
		reg = <0x00 0x04a00000 0x00 0x100>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 149 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	mcu_i2c0: i2c@4900000 {
		compatible = "ti,am64-i2c", "ti,omap4-i2c";
		reg = <0x00 0x04900000 0x00 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 2>;
		clock-names = "fck";
		status = "disabled";
	};
};