• Kumar Gala's avatar
    powerpc/e500mc: flush L2 on NAP for e500mc · aba11fc5
    Kumar Gala authored
    If we have an L2CSR register (e500mc) we need to flush the L2 before going
    to nap.  We use the HW flush mechanism provided in that register.
    
    The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
    any code in the kernel.  Additionally we didn't reuse the exist L2CR
    feature bit as this is intended for the 7xxx L2CR register and L2CSR
    is part of the new Freescale "Book-E" registers.
    Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    aba11fc5
idle_e500.S 2.2 KB