Add the DT nodes for the ICSSG0 and ICSSG1 processor subsystems that are
present on the K3 AM64x SoCs. The two ICSSGs are identical to each other
for the most part, with some of the peripheral pins from ICSSG1 not pinned
out. Each ICSSG instance is represented by a PRUSS subsystem node and other
child nodes.

The nodes are all added and enabled in the common k3-am64-main.dtsi
file by default. The MDIO nodes need pinctrl lines, and so should be
enabled only on boards where they are actually wired and pinned out
for ICSSG Ethernet. Any new board dts file should disable these if
they are not sure. These are disabled in the existing AM64x board dts
files to begin with.

The ICSSGs on K3 AM64x SoCs are very similar to the versions of the ICSSG
on K3 J721E and AM65x SR2.0 SoCs. The IRAM and BroadSize RAM sizes are all
identical to those on J721E SoCs. All The ICSSG host interrupts intended
towards the main Arm core are also shared with other processors on the SoC,
and can be partitioned as per system integration needs.

The ICSSG subsystem node contains the entire address space. The various
sub-modules of the ICSSG are represented as individual child nodes (so
platform devices themselves) of the PRUSS subsystem node. These include:
 - two Programmable Real-Time Units (PRUs)
 - two auxiliary PRU cores called RTUs
 - two Transmit Programmable Real-Time Units (Tx_PRUs)
 - Interrupt controller (INTC)
 - a 'memories' node containing all the ICSSG level Data RAMs
 - Real Time Media Independent Interface controller (MII_RT)
 - Gigabit capable MII_G_RT
 - ICSSG CFG sub-module providing two internal clock muxes, with the
   default clock parents also assigned using the assigned-clock-parents
   property.

The default names for the firmware images for each PRU, RTU and Tx_PRU
cores are defined as follows using the 'firmware-name' property (these
can be adjusted either in derivative board dts files or through sysfs at
runtime if required):
 ICSSG0 PRU0 Core    : am64x-pru0_0-fw   ; PRU1 Core    : am64x-pru0_1-fw
 ICSSG0 RTU0 Core    : am64x-rtu0_0-fw   ; RTU1 Core    : am64x-rtu0_1-fw
 ICSSG0 Tx_PRU0 Core : am64x-txpru0_0-fw ; Tx_PRU1 Core : am64x-txpru0_1-fw
 ICSSG1 PRU0 Core    : am64x-pru1_0-fw   ; PRU1 Core    : am64x-pru1_1-fw
 ICSSG1 RTU0 Core    : am64x-rtu1_0-fw   ; RTU1 Core    : am64x-rtu1_1-fw
 ICSSG1 Tx_PRU0 Core : am64x-txpru1_0-fw ; Tx_PRU1 Core : am64x-txpru1_1-fw

Note:
1. The ICSSG INTC on AM64x SoCs share all the host interrupts with other
   processors, so use the 'ti,irqs-reserved' property in derivative board
   dts files _if_ any of them should not be handled by the host OS.
2. There are few more sub-modules like the Industrial Ethernet Peripherals
   (IEPs), eCAP, PWM, UART that do not have bindings and so will be added
   in the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210919202935.15604-1-s-anna@ti.com