• Yazen Ghannam's avatar
    x86/cpu/AMD: Fix cpu_llc_id for AMD Fam17h systems · b0b6e868
    Yazen Ghannam authored
    cpu_llc_id (Last Level Cache ID) derivation on AMD Fam17h has an
    underflow bug when extracting the socket_id value. It starts from 0
    so subtracting 1 from it will result in an invalid value. This breaks
    scheduling topology later on since the cpu_llc_id will be incorrect.
    
    For example, the the cpu_llc_id of the *other* CPU in the loops in
    set_cpu_sibling_map() underflows and we're generating the funniest
    thread_siblings masks and then when I run 8 threads of nbench, they get
    spread around the LLC domains in a very strange pattern which doesn't
    give you the normal scheduling spread one would expect for performance.
    
    Other things like EDAC use cpu_llc_id so they will be b0rked too.
    
    So, the APIC ID is preset in APICx020 for bits 3 and above: they contain
    the core complex, node and socket IDs.
    
    The LLC is at the core complex level so we can find a unique cpu_llc_id
    by right shifting the APICID by 3 because then the least significant bit
    will be the Core Complex ID.
    Tested-by: default avatarBorislav Petkov <bp@suse.de>
    Signed-off-by: default avatarYazen Ghannam <Yazen.Ghannam@amd.com>
    [ Cleaned up and extended the commit message. ]
    Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
    Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
    Cc: <stable@vger.kernel.org> # v4.4..
    Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Fixes: 3849e91f ("x86/AMD: Fix last level cache topology for AMD Fam17h systems")
    Link: http://lkml.kernel.org/r/20161108083506.rvqb5h4chrcptj7d@pd.tnicSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    b0b6e868
amd.c 23.6 KB