Introduce the compatible string 'fsl,imx8ulp-edma' to enable support for
the i.MX8ULP's eDMA, alongside adjusting the clock numbering. The i.MX8ULP
eDMA architecture features one clock for each DMA channel and an additional
clock for the core controller. Given a maximum of 32 DMA channels, the
maximum clock number consequently increases to 33.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240323-8ulp_edma-v3-4-c0e981027c05@nxp.comSigned-off-by: Vinod Koul <vkoul@kernel.org>