• Christophe Leroy's avatar
    powerpc/8xx: Perf events on PPC 8xx · 75b82472
    Christophe Leroy authored
    This patch has been reworked since RFC version. In the RFC, this patch
    was preceded by a patch clearing MSR RI for all PPC32 at all time at
    exception prologs. Now MSR RI clearing is done only when this 8xx perf
    events functionality is compiled in, it is therefore limited to 8xx
    and merged inside this patch.
    Other main changes have been to take into account detailed review from
    Peter Zijlstra. The instructions counter has been reworked to behave
    as a free running counter like the three other counters.
    
    The 8xx has no PMU, however some events can be emulated by other means.
    
    This patch implements the following events (as reported by 'perf list'):
      cpu-cycles OR cycles				[Hardware event]
      instructions					[Hardware event]
      dTLB-load-misses				[Hardware cache event]
      iTLB-load-misses				[Hardware cache event]
    
    'cycles' event is implemented using the timebase clock. Timebase clock
    corresponds to CPU clock divided by 16, so number of cycles is
    approximatly 16 times the number of TB ticks
    
    On the 8xx, TLB misses are handled by software. It is therefore
    easy to count all TLB misses each time the TLB miss exception is
    called.
    
    'instructions' is calculated by using instruction watchpoint counter.
    This patch sets counter A to count instructions at address greater
    than 0, hence we count all instructions executed while MSR RI bit is
    set. The counter is set to the maximum which is 0xffff. Every 65535
    instructions, debug instruction breakpoint exception fires. The
    exception handler increments a counter in memory which then
    represent the upper part of the instruction counter. We therefore
    end up with a 48 bits counter. In order to avoid unnecessary overhead
    while no perf event is active, this counter is started when the first
    event referring to this counter is added, and the counter is stopped
    when the last event referring to it is deleted. In order to properly
    support breakpoint exceptions, MSR RI bit has to be unset in exception
    epilogs in order to avoid breakpoint exceptions during critical
    sections during changes to SRR0 and SRR1 would be problematic.
    
    All counters are handled as free running counters.
    Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
    Signed-off-by: default avatarScott Wood <oss@buserror.net>
    75b82472
reg_8xx.h 4.92 KB