• Will Deacon's avatar
    arm64: mm: report unhandled level-0 translation faults correctly · 7f73f7ae
    Will Deacon authored
    Translation faults that occur due to the input address being outside
    of the address range mapped by the relevant base register are reported
    as level 0 faults in ESR.DFSC.
    
    If the faulting access cannot be resolved by the kernel (e.g. because
    it is not mapped by a vma), then we report "input address range fault"
    on the console. This was fine until we added support for 48-bit VAs,
    which actually place PGDs at level 0 and can trigger faults for invalid
    addresses that are within the range of the page tables.
    
    This patch changes the string to report "level 0 translation fault",
    which is far less confusing.
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    7f73f7ae
fault.c 15.1 KB