• David Lechner's avatar
    dt-bindings: clock: Add new bindings for TI Davinci PLL clocks · b6e37ce2
    David Lechner authored
    This adds a new binding for the PLL IP blocks in the mach-davinci
    family of processors. Currently, only da850 has device tree support
    but these bindings can also work for other SoCs in this family just
    by adding new compatible strings.
    
    Note: Although these PLL controllers are very similar to the TI Keystone
    SoCs, we are not re-using those bindings. The Keystone bindings use a
    legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs
    have a slightly different PLL register layout and a number of quirks
    that can't be handled by the existing bindings, so the keystone bindings
    could not be used as-is anyway.
    Signed-off-by: default avatarDavid Lechner <david@lechnology.com>
    Reviewed-by: default avatarRob Herring <robh@kernel.org>
    Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
    b6e37ce2
pll.txt 2.38 KB